g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 1 - features : description : * low-power consumption. -active: 40ma icc at 55ns. -stand by : 5 m a (cmos input / output) 1 m a (cmos input / output, sl) * single +2.7 to 3.3v power supply. * equal access and cycle time. * 55/70/85/100 ns access time. * tri-state output. * automatic power-down when deselected. * multiple center power and ground pins for improved noise immunity. * individual byte controls for both read and write cycles. * available in 44pin tsopii package. the glt6100l16 is a low power cmos static ram organized as 65,536 words by 16 bits. easy memory expansion is provided by an active low ce and oe pin. this device has an automatic power ? down mode feature when deselected. separate byte enable controls ( ble and bhe ) allow individual bytes to be accessed. ble controls the lower bits i/o0 ? i/o7. bhe controls the upper bits i/o8 ? i/o15. writing to these devices is performed by taking chip enable ce with write enable we and byte enable ( ble / bhe ) low. reading from the device is performed by taking chip enable ce with output enable oe and byte enable ( ble / bhe ) low while write enable we is held high. pin configurations : glt6100l16 a 4 1 2 3 4 5 6 7 9 10 12 13 14 vcc 8 15 16 17 18 19 20 21 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 ce i/o 0 oe ble nc 22 23 34 11 vcc we a 3 a 2 a 1 a 0 i/o 1 i/o 2 i/o 3 vss i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc a 11 a 10 a 9 a 8 nc i/o 8 i/o 9 i/o 10 i/o 11 vss i/o 12 i/o 13 i/o 14 i/o 15 bhe a 7 a6 a 5 function block diagram : row select a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 memory array 1024 x 1024 pre-charge circuit i/o circuit column select a 10 a 11 a 12 a 13 a 14 a 15 data circuit data circuit vcc vss we oe ble bhe ce i/o 8 - i/o 15 i/o 0 - i/o 7
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 2 - pin descriptions: name function a 0 ? a 15 address inputs ce 1 and ce 2 chip enable input oe output enable input we write enable input i/o 0 ? i/o 15 data input and data output v cc 3v power supply gnd ground nc no connection truth table: ce oe we ble bhe i/o0-i/o7 i/o8-i/o15 power mode h x x x x high-z high-z standby standby l l h l h data out high-z active low byte read l l h h l high-z data out active high byte read l l h l l data out data out active word read l x l l l data in data in active word write l x l l h data in high-z active low byte write l x l h l high-z data in active high byte write l h h x x high-z high-z active output disable l x x h h high-z high-z active output disable absolute maximum ratings* parameter symbol minimum maximum unit voltage on any pin relative to gnd vt -0.5 4.6 v power dissipation p t - 1.0 w storage temperature (plastic) tstg -55 +150 c temperature under bias tbias -40 +85 c *note : stresses greater than those listed above absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 3 - recommended operating conditions ( ta = -25 c to + 85 c** ) parameter symbol min typ max unit v cc 2.7 3.0 3.3 v supply voltage gnd 0.0 0.0 0.0 v v ih 2.2 - v cc +0.5 v input voltage v il -0.5* - 0.6 v * v il min = -2.0v for pulse width less than t rc /2. ** for industrial temperature. dc operating characteristics ( vcc=2.7 to 3.3v , t a =-25 c to + 85 c) 55 70 85 100 parameter sym. test conditions min max min max min max min max unit input leakage current ? i li ? v cc = max, vin = gnd to v cc 1 1 1 1 m a output leakage current ? i lo ? ce =v ih or v cc = max, v out = gnd to v cc 1 1 1 1 m a operating power supply current i cc ce =v il ,v in =v ih or v il , i out =0 3 3 3 3 ma i cc1 i out = 0ma, min cycle, 100% duty 40 35 30 30 ma average operating current i cc2 ce 0.2v i out = 0ma, cycle time=1 m s, 100% = duty 3 3 3 3 ma standby power supply current(ttl level) i sb ce =v ih 0.5 0.5 0.5 0.5 ma glt6100l16ll 5 5 5 5 m a standby power supply current (cmos level) i sb1 ce 3 v cc -0.2v v in 0.2v or v in 3 v cc -0.2v glt6100l16sl 1 1 1 1 m a output low voltage v ol i ol = 2 ma 0.4 0.4 0.4 0.4 v output high voltage v oh i oh = -2 ma 2.4 2.4 2.4 2.4 v data retention parameter sym. test conditions min. max. unit v cc for data retention v dr 2.0 - v data retention current i ccdr 1 m a chip deselect to data retention time t cdr 0 - ns operating recovery time (2) t r ce 3 v cc -0.2v v in 3 v cc -0.2v or v in 0.2v t rc - ns
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 4 - data retention waveform (ta = -25 c to + 85 c) data retention mode vcc ce v dr v dr >= 2.0v t r t cdr vcc_typ vcc_typ v ih v ih ac test conditions ac test loads and waveforms c l * ttl output load condition *including scope and jig capacitance 55ns / 70ns / 85ns c l = 30pf + 1ttl load load 100ns c l = 100pf + 1ttl load read cycle (9) ( vcc=2.7v to 3.3v, t a = -25 c to + 85 c) 55 70 85 100 parameter symbol min max min max min max min max unit note read cycle time t rc 55 70 85 100 ns address access time t aa 55 70 85 100 ns chip enable access time t ace 55 70 85 100 ns output enable access time t oe 35 40 40 50 ns output hold from address change t oh 10 10 10 10 ns chip enable to output in low-z t lz 10 10 10 10 ns 4,5 chip disable to output in high-z t hz 25 30 35 40 ns 3,4,5 output enable to output in low-z t olz 5 5 5 5 ns output disable to output in high-z t ohz 25 25 30 35 ns ble , bhe enable to output in low-z t blz 5 5 5 5 ns 4,5 ble , bhe disable to output in high-z t bhz 25 25 30 35 ns 3,4,5 ble , bhe access time t ba 35 40 40 50 ns input pulse levels 0.6v to 2.2v input rise and fall time input and output timing reference level 5 ns 1.4v
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 5 - timing waveform of read cycle 1 (address controlled) d out t rc address t oh t aa previous data valid data valid timing waveform of read cycle 2 (14~16) d out t rc address t oh t aa t lz t oe t ba t olz t blz t hz t bhz t ohz t oh data valid high - z ce ble / bhe oe write cycle (11) ( vcc=2.7v to 3.3v, t a = -25 c to + 85 c) 55 70 85 100 parameter symbol min max min max min max min max unit note write cycle time t wc 55 70 85 100 ns chip enable to write end t cw 50 60 70 80 ns address setup to write end t aw 50 60 70 80 ns address setup time t as 0 0 0 0 ns write pulse width t wp 45 50 60 70 ns write recovery time t wr 0 0 0 0 ns data valid to write end t dw 25 30 35 40 ns data hold time t dh 0 0 0 0 ns write enable to output in high-z t whz 25 30 35 40 ns output active from write end t ow 5 5 5 5 ns ble , bhe setup to write end t bw 50 60 70 80 ns
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 6 - timing waveform of write cycle 1 (address controlled) (22~25,28) d out t wc address t aw t wr ce ble / bhe we t cw t bw t as t wp t dw t dh t ow high-z high-z d in timing waveform of write cycle 2 ( ce controlled) (22~26,28) d out t wc address t aw t wr ce ble / bhe we t cw t as t bw t wp t dw t dh t whz t lz high - z high - z high - z d in
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 7 - timing waveform of write cycle 3 ( ble / bhe controlled) (22~26,28) d out t wc address t aw t wr ce ble / bhe we t cw t as t bw t wp t dw t dh t whz t blz high - z high - z high - z d in
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 8 - notes : 1. l-version includes this feature. 2. this parameter is samples and not 100% tested. 3. for test conditions, see ac test condition. 4. this parameter is tested with cl = 5pf. transition is measured 500mv from steady ? state voltage. 5. this parameter is guaranteed, but is not tested. 6. we is high for read cycle. 7. ce and oe are low for read cycle. 8. address valid prior to or coincident with ce transition low. 9. all read cycle timings are referenced from the last valid address to the first transition address. 10. ce or we must be high during address transition. 11. all write cycle timings are referenced from the last valid address to the first transition address. 12. we are high for read cycle. 13. all read cycle timing is referenced from the last valid address to the first transition address. 14. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition referenced to v oh or v ol levels. 15. at any given temperature and voltage condition t hz (max.) is less than t lz (min.) both for a given device and from device to device. 16. transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 17. device is continuously selected with ce = v il . 18. address valid prior to coincident with ce transition low. 19. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read write cycle. 20. for test conditions, see ac test condition. 21. all write timing is referenced from the last valid address to the first transition address. 22. a write occurs during the overlap of a low ce and we . a write begins at the latest transition among ce and we going low: a write ends at the earliest transition among ce going high and we going high. t wp is measured from the beginning of write to the end of write. 23. t cw is measured from the later of ce going low to end of write. 24. t as is measured from the address valid to the beginning of write. 25. t wr is measured from the end of write to the address change. 26. if oe , ce and we are in the read mode during this period, the i/o pins are in the output low-z state. 27. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 28. if ce goes low simultaneously with we going low or after we going low, the outputs remain high impedance state. 29. d out is the read data of the new address. 30. when ce is low : i/o pins are in the outputs state. the input signals in the opposite phase leading to the output should not be applied. 31. for test conditions, see ac test condition.
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 9 - ordering information part number speed power package GLT6100L08LL-55TC 55ns normal tsopii 32l glt6100l08ll-70tc 70ns normal tsopii 32l glt6100l08ll-85tc 85ns normal tsopii 32l glt6100l08ll-100tc 100ns normal tsopii 32l glt6100l08sl-55tc 55ns normal tsopii 32l glt6100l08sl-70tc 70ns normal tsopii 32l glt6100l08sl-85tc 85ns normal tsopii 32l glt6100l08sl-100tc 100ns normal tsopii 32l parts numbers (top mark) definition : glt 6 100 l 16 ll- 55 tc note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 64k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : 2.5v n : 2.1v config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) st : stsop (type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp ll : low low power l : low power sl : super low power
g-link glt6100l16 ultra low power 64k x 16 cmos sram may 2000(rev. 0.3) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation, taiwan 6f no. 24-2, industry e. rd. iv, science based industrial park, hsin chu, taiwan. - 10 - package information 44 pin small outline j-form package (tsopii)
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